
BR34L02FV-W
Technical Note
The open drain interface is recommended for the SDA port in the I C BUS. However, if the Tri-state CMOS interface is
● Microcontroller connection
○ Concerning Rs
2
applied to SDA, insert a series resistor (Rs) between the SDA pin of the device and the pull up resistor R PU is
recommended, since it will serve to limit the current between the PMOS of the microcontroller, and the NMOS of the
EEPROM. Rs also protects the SDA pin from surges. Therefore, Rs is able to be used though open drain inout of the
SDA port.
ACK
R PU
R S
SCL
SDA
'H'OUTPUT OF
CONTROLLER
“L” OUTPUT OF EEPROM
CONTROLLER
EEPROM
The “H” output of controller and the “L” output of
EEPROM may cause current overload to SDA line.
Fig.44 I/O Circuit
Rs Maximum
The maximum value of Rs is determined by following factors.
① SDA rise time determined by R PU and the capacitance value of the BUS line (CBUS) of SDA must be less than tR. In
addition, the other timings must be within the timing conditions of the AC.
② When the output from SDA is Low, the voltage of the BUS at A
is determined by R PU, and Rs must be lower than
the input Low level of the microcontroller, including recommended noise margin (0.1V CC ).
V CC
R PU
A
(V CC -V OL )×R S
R PU +R S
+ V OL +0.1V CC ≦ V IL
R S
I OL
V OL
∴ R S ≦
V IL -V OL -0.1V CC
1.1V CC -V IL
×
R PU
BUS
CAPACITANCE
Examples : When V CC =3V V IL =0.3V CC V OL =0.4V R PU =20k ?
V IL
CONTROLLER
EEPROM
According to ② R S ≦
0.3×3-0.4-0.1×3
1.1×3-0.3×3
×
20×10 3
Fig.46 I/O Circuit
≦ 1.67 [ k ? ]
Rs Minimum
The minimum value of Rs is determined by the current overload during BUS conflict.
Current overload may cause noises in the power line and instantaneous power down.
The following conditions must be met, where “I” is the maximum permissible current, which depends on the Vcc line
impedance as well as other factors. “I” current must be less than 10mA for EEPROM.
Vcc
R S
≦
I
R PU
R S
"L" OUTPUT
∴ R S ≧
Vcc
I
Examples: When V CC =3V, I=10mA
"H" OUTPUT
MAXIMUM
CURRENT
R S
≧
3
10×10 -3
CONTROLLER
EEPROM
≧ 300 [ ? ]
Fig.47 I/O Circuit
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2009.04 - Rev.A